Programmable logic devices (PLDs) that implement the use of non-volatile elements are well known. In the early development of PLDS, an array was used which basically consisted of a grid of conductors forming rows and columns with a fusible link at each cross point. The data output was programmed to be the desired combinatorial function of the device's address signals. Later, integrated circuits (ICs) were designed specifically for the purpose of generating sum-of-product (SOP) logic. The non-volatile memory elements were connected within the IC in such a way as to form logical AND gates (product terms). By connecting the outputs of two or more AND gates as inputs to a logical OR gate, the output of the OR gate would constitute an SOP logic function. The SOP form was chosen because it is widely known in the art that a combinational function of any complexity may be reduced to SOP form. Therefore, any such combinatorial function may be realized within such an IC, if there are sufficient such AND and OR gates available within the IC.
Further evolution of PLDs involved the addition of configuration bits (CBs) to allow programmable alteration of the output format of the SOP function. This led to the development of output logic macrocells (OLMCs). The OLMC is made of programmable logic circuits that can be configured either for a combinational output or input or for a registered output. In the registered mode, the output comes from a flip-flop. OLMC combinational mode configurations are automatically set by programming. FIG. 4 shows a block diagram of a typical OLMC 500 that has two configuration bits. The first configuration bit, 501, determines whether the OEMC operates in registered mode (through the flip-flop 504) or in combinational mode. The second configuration bit, 502, determines whether the output is "active-LOW" or "active-HIGH". The 1 of 4 multiplexer 505 connects one of its four input lines to the output tristate buffer 507 based on the states of the two configuration bits, 501 and 502. The 1 of 2 multiplexer 506 connects either the output 508 of the tristate buffer 507 or the Q output of the flipflop 504 back through a buffer 509 to the programmable array. In a typical PLD, several OLMCs are used, one for each SOP term, with a common clock pin for all OLMC registers. More recent product term based PLDs have included many more configuration bits within each OIMC in order to increase device flexibility without increasing the number of product terms. In addition to output polarity and registered vs. combinatorial output signal selection, these CBs perform functions such as: routing individual product terms for use other than as OR gate inputs, selecting between alternative clock, set and preset sources for device registers, and selecting between alternative output enable functions.
Including many CBs for each OLMC results in OLMCs that can be configured in any of a large number of ways. (For N binary level CBs, up to 2.sup.N such configurations may be possible.) One of the difficulties involved with a large amount of configurations is that the IC manufacturer has to program each OLMC to each of the possible configurations (potentially 2.sup.N combinations), and test each configuration to insure that all of the configurations operate correctly. Although the amount of testing may be somewhat reduced by programming and testing CBs that control independent functions separately, testing CBs constructed from non-volatile elements may be prohibitively expensive. For example, some such non-volatile elements take 100 msec or longer to erase and reprogram. Non-volatile element programming often takes even longer than erasure. As the testing of high density, performance PLDs often has a cost that is based on time, any additional time required for erasing and reprogramming the device adds more to the cost of producing the device. It is therefore beneficial to be able to minimize the amount of time required to erase and reprogram the CBs during the testing phase of manufacturing the PLDS.
One method that can be used to provide a faster means for reprogramming the CBs is shown in FIG. 5. In this method, a bistable configuration latch (CL) 603 is included within the IC for each configuration bit (CB) 604. The output of the CL 603 is then used by the macrocell to generate the configuration control signal 605. Upon initial power-up of the IC, the Sense Enable Signal 601 is pulsed, allowing the state of the CL 603 to be set by the non-volatile element of the CB 604. Subsequently, the CL 603 may be set by a separate data input signal by raising the Override Enable Signal 602, thereby overriding the non-volatile data previously stored in the latch. Simple bistable latches can be set in a few nanoseconds or less, so this significantly reduces the time required for changing the CB's logic state. By including a CL for each CB, the time required for testing CB operation is no longer limited by CB reprogramming, but rather by how many test vectors need to be asserted for each configuration and how quickly the vectors can be applied. Since advanced test equipment can apply the test vectors extremely fast, the overall time and cost of configuration bit testing can be significantly reduced.
However, previous designs of such CL test capability have required the use of many external device pins to provide input data for the latches. The large number of pin connections complicates test hardware, adding time and cost to the development and sustaining of such hardware. Many methods have been developed for addressing other IC test requirements, some of such methods use a minimal number of external device pins. One such method is described in IEEE specification 1149.1, commonly referred to as the Joint Test Action Group (JTAG) specification. FIG. 6 shows a block diagram of the external pin connections and internal circuitry required to implement JTAG testing. This method teaches the use of an Instruction Register (IR) 701, a Test Access Port (TAP) 704, a TAP controller 703 containing a TAP State Machine, and Test Data Registers (TDRs) 702 to implement test functions using a standardized 4 pin (or optionally 5 pin) external interface. The 4 (or 5) pin external interface is known as the Test Access Port (TAP) 704. Besides the small number of external pins required, this JTAG method also has the advantage of being useful for a wide number and variety of device test and operational functions. And since this method is standardized, development of test system hardware and software to support new test features using this method is relatively simple and therefore inexpensive for both the device manufacturer and the device user. More details regarding the implementation of the JTAG method will be provided below.